As for technique examined by the inventor, there is the following technique in the PLL circuit, for example.
In Japanese Patent Application Laid-Open Publication No. 2001-257567 (Patent Document 1), a circuit configuration of a voltage controlled oscillator enabling generation of a clock signal having small jitter even when a power source voltage fluctuates, in the PLL circuit including a phase comparator, a frequency comparator and a voltage controlled oscillator is shown, for example. Specifically, a configuration in which, with respect to a configuration including a ring oscillator and capacitance mutually connected in parallel and a MOS transistor controlling an oscillation frequency by controlling a power source voltage (current) thereof, a second means for controlling the oscillation frequency according to a phase comparison result is provided. This second means is realized by capacitance capable of switching connection/disconnection with respect to the ring oscillator, and according to the phase comparison result, when the capacitance is connected, the oscillation frequency lowers with increase of a load and when the capacitance is disconnected, the opposite operation is performed.
And, in Japanese Patent Application Laid-Open Publication No. 2005-252723 (Patent Document 2), a PLL circuit having a configuration in which the comparison result of the frequency comparator is reflected to a VCO (Voltage Controlled Oscillator) through a processing by an integration circuit, a comparator and a gain adjustment circuit is shown. This frequency comparator compares and determines high and low of the frequency by observing change of a phase of an input clock using three phase periods obtained from three phase clocks from the VCO as a reference. By reflecting the result of such frequency comparator to the VCO through various processes described above, even if false detection of the frequency comparator occurs, influence thereof can be reduced.